Last Ask-Away-Friday, I received the following question:

*“Do you always follow the recommendations for decoupling in IC-data sheets?”*

The short answer is: mostly

The main reason is that you may assume that the decoupling network that the IC manufacturer prescribes has been tested and that the IC will work as expected.

It sometimes looks like IC manufacturers prescribe 100 nF per power supply pin by standard. The reason is that it simply does the job in most cases. For example, a single 100 nF 0402 X7R capacitor has an impedance of less than 1 Ohm between ± 2 MHz and ±50 MHz. Combined with some bulk capacitance, the frequency spectrum from DC up to beyond the working frequency of the IC is covered.

Of course, there is nothing against doing it better. And sometimes, you cannot avoid designing a decoupling network.

Here are some tips for designing decoupling networks:

- Always simulate or calculate the required decoupling of an IC. Every IC has its own specific needs for decoupling, which may vary over frequency.
- Always simulate or calculate the impedance of the decoupling network. Add the impedances of traces and vias for a truer outcome at high frequencies.
- The value of a capacitor may be drastically reduced by applying a DC bias to the capacitor.
- Ferrite beads may already have an impedance of several tens of Ohms around 1 MHz.This means that after a ferrite bead, you will have to add more capacitance to stay below the maximum required impedance of the decoupling network around this frequency.
- A capacitor’s ESR is not always constant over frequency. Bear this in mind when the design for a decoupling network relies heavily on the ESR of capacitors used.
- For complex decoupling networks I usually replace the frequency domain calculations for time domain calculations. This time domain approach takes the guesswork out of the equation, which makes it easier to guarantee that a decoupling network will perform as expected, especially for higher frequencies.